Honored ContributorI got Cyclone II FPGA starter Kit. I want to create an entity that will handle the seven segment in it in all my projects. something I can just add and it will automatically be assigned to the correct pins and everything. how do I do it?
maybe even make it recognize what is the kit I currently use and be assigned accordingly.
Honored ContributorI am afaid you can't go that automated. You need to manually assign the pins. The kit itself is never visible to HDL.
Create your 7 segment entity, decide its functionality if you haven't got one ready-made then assign pins as appropriate. You can connect switches to the input of your module so that it can be used all over your project for whatever purpose. edit: some compilers accept pin attributes in code levelHonored Contributorno way to add a TCL script? (I heard the word TCL and thought: "SHINY" no clue what is it or how to use it) though I am aware to Google but I am sick kinda lazy and because I'm a freaking software guy and not really sure what to look I just lack the common language (with compulsory army enlistment you don't always get were you want (or even close) )I do VHDL now I like it alot but still very confused. perhaps make some kind of project.ini for each of my project and and every such entity I make will include script that will access to the ini file recognize what device I use and other configurations and assign my pins accordingly?
Honored ContributorI have been doing vhdl for 15 years now and don't how to TCL things around, I always use the quartus GUI, I am as lazy as you are though finished army service long long time ago in Saddam's army - true 3yrs plus. I still have a bullet scar in my left arm
Honored ContributorPlease consider, that location assignments have to be done to pins of the top level entity. An 7-Segment module or entity hasn't anything to do with top-level pins. If you accept to use identical pin names in all designs, you can simply copy the assignment tcl lines from an example design's *.qsf file and import them to your new design.
Honored ContributorI was never able to ferret the pin-assignment details from the Altera docs, but a co-worker did so: here is an example of embedding pin assignments in Verilog code:
//System input SYNC_IN /* synthesis altera_chip_pin_lc = "5"*/; output SYNC_OUT /* synthesis altera_chip_pin_lc = "39"*/; input SW_2 /* synthesis altera_chip_pin_lc = "18"*/; input SW_1 /* synthesis altera_chip_pin_lc = "21"*/; output LED1 /* synthesis altera_chip_pin_lc = "37"*/; output LED2 /* synthesis altera_chip_pin_lc = "22"*/; //SRAM inout [15:0] SR_DTA /* synthesis altera_chip_pin_lc = "218,226,230,231,232,233,234,235,188,189,194,195,196,197,200,201"*/; output SR_OEN /* synthesis altera_chip_pin_lc = "219"*/; output SR_WEN /* synthesis altera_chip_pin_lc = "187"*/; output SR_CEN /* synthesis altera_chip_pin_lc = "202"*/; output [18:0] SR_ADR /* synthesis altera_chip_pin_lc = "236,224,223,221,237,238,239,240,4,182,183,184,185,186,203,217,216,214,207"*/; Wade HasslerHonored Contributorthis unfortunately requires Synplify software that I cannot access.
Honored ContributorHonored ContributorSome info on tcl:
http://tmml.sourceforge.net/doc/tcl/index.html http://www.doulos.com/knowhow/tcltk/ I would say it's worth looking at - particularly if you use Modelsim and get frustrated with the buggy GUI. I don't think it's your salvation in this instance. I'm sure you could write a script to intelligently patch in your code and pin assignments to your VHDL but I wouldn't suggest that it would be a quick fix for your problem if you are totally new to Tcl.
