I would like to know the assembly tolerance value for PN#10M08SAM153I7G and PN#10M08SAU169I7G.

Hi Raja,

In the below link (Packaging specification and dimension page), Intel did mention the tolerance for the package outline.

Eg: the min and max value stated in the page is the tolerance for the package outline.

https://www.intel.com/content/www/us/en/programmable/support/literature/lit-index/lit-pkg/package.html?family=MAX_10

Meanwhile,

Sorry to let you know that Intel FPGA do not provide support for PCB footprint symbols for FPGA and CPLD device families, similar to configuration devices.

However, we will continue the support by providing the schematic symbol which you can download from the link above. You could have the schematic symbol in .olb format from the link below:

https://www.intel.com/content/www/us/en/programmable/support/support-resources/download/board-layout-test/pcb/pcb-cadence.html

Thank you.

Regards,

Aiman