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Altera_Forum's avatar
Altera_Forum
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15 years ago

I think 12mA pins are not driving properly. How to go about?

hello all,

I am new to this forum.

I am using arrea gx for my design. I have 2 cypress rams connected to fpga I/O s. One of those is not functioning as expected. when i was verifying the pin assignments for those rams I found that for pins (byte controls) are assigned the pins with 12mA driving capacity. Out of these, two pins are functioning properly (i can make from the output i got). In case of the other RAM these byte controls are connected to 24mA i/o pins of FPGA and is working fine.

I have worked with these rams earlier also and i have confirmed that ram is functional. So I am suspecting on 12mA pins. I have monitored signals on those I/O pins and looks to be 'ok' (3.3V for logic '1' and 0V for 0). ut I can simply suspect on driving capability is the problem as out of these 4 pins 2 are working fine. Can you please help me to identify wat cud b the prblm.? Making any changes in the assignment editor will help?

FYI: I cannot change board design and I cannot assign some other FPGA pins to this ram.

Thank you.

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    The main effect when driving 24 versus 12 mA to a LVCMOS load is reducing the edge rise- and fall-times, most likely introducing some overshoot if no additional termination is present, and generally reducing the effective signal delay.

    Personally I try to use high drive strength only if it's absolutely needed, e.g. for clock signals that need fast edges. In any case, it's better to check the waveforms at the load with a suitable active oscilloscope probe.

    If a particular signal seems to have problems with 12 mA drive strength, this is mainly indicating a timing problem. Increasing the drive strength is only one of many ways to handle it.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thank you.

    I have monitored the signals at the RAM pins using CRO. Signals are good. Anyway, I will check it once again today. I have even tried assigning 'maximum current' in assignment editor. Did not help :( If it is the problem with some delay or rise/fall time, how can I specify those constraints? Assignment editor?

    Regards,

    kthurst.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Arria has diiferent maximum current strength in row and column banks. Maximum current is either 12 or 24 mA.