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Daniel_DD's avatar
Daniel_DD
Icon for New Contributor rankNew Contributor
4 years ago

I Reconfig Clock FPGA

I am in the early stages of designing a 100 Gb F tile. Can i reconfig clock come from a pll or does it have to be its own dedicated clock from the fabric?
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

Hi,

Can you please clarify which clock signal are you talking about in the diagram? The Reference clk(s) at the bottom? Or the i_clk_rx and i_clk_tx ?


Regards