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Finees's avatar
Finees
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2 years ago
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I_PIN_PERST_N signal is not assignable in Agilex 7

Hi I am building a PCIe controller on Agilex 7 (AGIB027R31B2E3). I want to assign the I_PIN_PERST_N signal in bank 13C. In the Pin Planner, I try to assign pin Y21 as the PERST_N signal, but I get a...
  • Wincent_Altera's avatar
    2 years ago

    Hi,


    In the Pin Planner, I try to assign pin Y21 as the PERST_N signal, but I get a message that the pin is not assignable.

    >> if you assign the pin based on the example design, did you see any error ?

    >> is there any specific reason you change the pin location ?


    But if I don't assign the pin, I get the following Critical Warning: "There is no accurate pin location assignment(s) for 1 of the 693 total pins. To see the pin list, refer to the I/O assignment warnings table in the installer report."

    >> According to the user guide , If the F-tile is unused, or the F-tile is used but PCI Express* is unused, tie to GND.

    >> Did you try to Use a level translator to fan out and change the 3.3-V open-drain nPERST signal from the PCIe* connector to the 1.8-V input of each F-tile transceiver that is used on the board. Provide a 1.8-V pull-up resistor for this input pin as the nPERST signal from the PCIe* connector is an open-drain signal. You must pull up the 3.3-V PCIe* nPERST signal on the adapter card.

    >> PERST# should be connected between the host slot and our device as shown in our dev kit schematic:

    https://www.intel.com/content/dam/altera-www/global/en_US/support/boards-kits/agilex/f-fpga/agilex-f-fpga-dk-2v-es.pdf


    Regards,

    Wincent_Intel