I need link to some very basic parameters of different FPGAs

You'll get the same things with Xilinx (and in some cases worse documentation and worse tools).

But what are your requirements? FPGAs are designed to be synchronous - so as long as you know what data throughput you need, you then know what clock you need, and as long as it's < 200 MHz inside the FPGA - there wont be a problem ( < 300 Mhz requires more effort, and > 300 Mhz will require lots of effort). Then estimate your memory requirements, DSP resources and Pinout - then you can easily decide what part to take. Because you know your clock speed, you know the reg -> reg delay requirements, and you let the fitter put all the effort in to make it work. Doesnt meet timing? modify your code to improve the pipelining.

FPGAs are not very good at asynchronous circuits - so why would you care about delays through luts? using luts to delay signals is a bad idea.

Altera could specify routing delay all they want - but it's pretty useless when someone decides to put 10 luts between two registers and cant acheive a clock speed any more than 50 Mhz. People are not drawing schematics at the gate level, they are writing code at the behavioural level.