Forum Discussion
Altera_Forum
Honored Contributor
10 years agoSo in another words, unless I stop and learn Quartus II, input all the circuits, do the simulation, I won't know whether it will work with certain device. Then I cannot even do the cost estimation to decide what approach I should use.
I am an old time designer that actually relies on real circuit data to design circuits. I design plenty of complicated digital hardware. I know how to estimate delay due to signal length, buffer delay and can estimate timing and speed easily just by simple addition. To me there is something wrong with this picture that people get away with this BASIC common sense knowledge and totally at the mercy of a simulation program. I am not a FPGA engineer, but many times in the past I fix FPGA programs designed by supposedly a "FPGA engineer". case in point, our system had intermittent problem that I traced down to the "FPGA engineer" drive the reset of the DFF with combination logic. IN AHDL, it is like dff.r= a+b+c. BUT in real life, A, B and C can have condition that A goes low before B goes high and create a glitch and reset the DFF intermittently. These are REAL circuit, not a program, this is REAL CIRCUIT that has timing. Experience people can spot this in a heart beat. But it would not be apparent. Maybe that's one of the reason why there are robust circuit of error detection and resend data to hide these problems. Far as I concern, this is SAD. I did AHDL in old Quartus in the pass, I am doing cost estimation and come up with a design approach. I wasted 5 days on this forum and I am not better off than 5 days ago.( Well I know what I cannot get out of Altera now). I cannot even tell whether I can use Arris II or I have to go to Stratix. this is sad. I might have to try Xilinx and see whether they are any better. Altera should just waste a page and just give out the data of these basic building blocks. Sounds like you can force the compiler to use RCLK or PCLK in very specific quadrant/region to estimate the prop delay. Just PUT the delay of these clocks, I/O buffer on the datasheet and let people do the estimation!!! Specify the speed of the trace like 5" per nS time!!! It's not that hard and it's not that hard for people to do addition!!! regard to temperature, You can estimate using the slowest speed!!!