I need link to some very basic parameters of different FPGAs

The problem is its not the register thats the problem timing, its the routing that causes the delay. Im sure you'll find a quote in most of the handbooks about the theoretical max speed of the rams, registers etc, but these are stupidly high and at a speed you would never reach in reality (figures like 400MHz for stratix 4 parts for example).

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regarding to NAND, AND, OR, NOR, this is just the most basic building blocks of random logics that if you know the spec, you can estimate others like MUX, ALU etc.

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THis again is meaningless - like I said, each design is made of LUTs, so a 2 to 1 mux can be done in a single LUT, but a 4 to 1 may be a 2 luts (or 1 LUT for newer devices). THen you have synthesis optimisation that may merge some of your logic together or minimise it. Then the fitter has to link all the LUTs together - you see where Im going. And because it uses a random seed for the fit the delay through the logic can vary with every build. This is where the timing analyser comes in and checks your design meets high and low temperature timing requirements.