I need link to some very basic parameters of different FPGAs

Data given by ASIC vendors includes tables for io timing requirements and fmax since these are fixed at fabrication.

FPGA vendors do not give such data since io timing is configurable to some extent(based on your io timing statements in sdc file).

On the other hand FPGA fabric registers are left at mercy of fitter routing and need not be known to user but overall fmax achievable may be given for specific design types as an idea.

There is no point to know tSU/tH/tCO of any fabric registers as the job is left for timing tool to achieve them across the rtl chain.

For io registers you can get them after compilation of a given design (in the datasheet section of timing report).

io toggle rate may be given as it may restrict fmax independent of register timing restriction