Honored Contributor
Honored ContributorI really don't get it, a flip flop is a simple basic unit, how can you not have a max clock speed, no clock to Q delay? Every flip flop in the pass have spec. there is always data setup time and hold time to clock. How can there is no specification? If everything depends on the design, then I can make a MAX run as far as the Stratix just by design!!!
I spent days reading, and I spend time typing 4 pages in another post here just to find out there is no spec? this is hardware with real wires and transistors that limit the rise time and fall time that can quantify by prop delay. I just cannot see how people can design without these specs. Do you just TRUST the simulation? Everything is based on simulation? regarding to NAND, AND, OR, NOR, this is just the most basic building blocks of random logics that if you know the spec, you can estimate others like MUX, ALU etc. What I asked are very very basic spec that EVERY logic datasheet specifies. Do you mean if I know my design need to have pipeline registers with simple logics in between. Instead of calculating the max frequency by adding the 1) clock to Q delay 2) delay of a few logic gate 3) data setup time of D input to the following clock. to get the max frequency. I have to write the program and simulate the whole thing to get a SIMPLE answer that I can do it in 1 minute to decide whether the particular FPGA and the speed grade can work for me if I have the few basic spec? this is SERIOUSLY WRONG. No offense.
