I need link to some very basic parameters of different FPGAs

There are simple answers here:

1. You can set the clock to whatever you want/need it to be for the data rate you need on the IO.

2. It depends on your design

3. It depends on your design

4. It depends on your design

5. It depends on your design.

6. The FPGA has no gates. Only LUTs - hence the Tpd of a single gate through a LUT is meaningless, because gates dont exist. And the timing will depend on your design

7. Level reset (Altera recommends Async assert, sync de-assert) - Xilinx on the other hand recommend sync resets only

8. Yes.

As you will see, the "it depends on your design" is key here. Altera publish maximum theoretical speed, but its unlikely you will ever get near these speeds.

edit: because i was wrong

last edited by tricky (http://www.alteraforum.com/forum/posthistory.php?p=200677); Today at 08:26 AM.