I instantiaze a pll with 4 output clock,but when I use Derive PLL Clocks command in Timing Analyzer, it only derive two generated clock?

altpll1 altpll1_inst (

.inclk0 ( chip_clk ),//20Mhz

.c0 ( sys_clk ), //400Mhz

.c1 ( uart_clk ), //25Mhz

.c2 ( clk_50M ), //50Mhz

.c3 ( clk_30M ),//30Mhz

.locked ( locked_sig )

);

according the route " Timing Analyzer->constraints->Create Generated clock "

to open "Create Generated Clock" window ,

and the open the ->source window

there are just the output clock clk[2] and clk[3] of the pll,where is the clk[0] and clk[1] of the pll?

by the way the ouput clk[0] is 400Mhz, and the ouput clk[1] is 25Mhz ,

and after run the create generate clock command ,there are only

the generate clock clk[2] ,cllk[3], what is the reason ?

​