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zlan01
New Contributor
New ContributorI instantiaze a pll with 4 output clock,but when I use Derive PLL Clocks command in Timing Analyzer, it only derive two generated clock?
altpll1 altpll1_inst ( .inclk0 ( chip_clk ),//20Mhz .c0 ( sys_clk ), //400Mhz .c1 ( uart_clk ), //25Mhz .c2 ( clk_50M ), //50Mhz .c3 ( clk_30M ),//30Mhz .locked ( locked_sig ...
zlan01New Contributor
New Contributoroh, perhaps because I only do synthesis step, and do not do the fitter step
