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zlan01's avatar
zlan01
Icon for New Contributor rankNew Contributor
6 years ago

I instantiaze a pll with 4 output clock,but when I use Derive PLL Clocks command in Timing Analyzer, it only derive two generated clock?

altpll1 altpll1_inst ( .inclk0 ( chip_clk ),//20Mhz .c0 ( sys_clk ), //400Mhz .c1 ( uart_clk ), //25Mhz .c2 ( clk_50M ), //50Mhz .c3 ( clk_30M ),//30Mhz .locked ( locked_sig ...
Rahul_S_Intel1's avatar
Rahul_S_Intel1
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hi ,

When I made a simple PLL and try to put the list fro the name finder , I can see all the out put from the PLL . May I know is that is a problem for you . The same is not view by you

Regards,

Rahul S