i dont understand this code, need your help

i found this code on the internet, they write by verilog, but im not familiar with verilog (just know about vhdl), so few things in this code that i dont understand and i need your help

/// reset //////////////////////////////////////						
//state machine start up	
wire reset; 
// reset control
assign reset = ~KEY;
///////////////////////////////////////////////
// state variable 
reg  state ;
//oneshot gen to sync to audio clock
reg last_clk ; 
// output to audio DAC
reg signed  audio_outL, audio_outR ;
// input from audio ADC
wire signed  audio_inL, audio_inR;
		
/// memory for phase shifter /////////////////////////////////////////
//memory control
reg we; //write enable--active high
wire  read_data; 
reg   write_data;
reg  addr_reg;
//pointers into the shift register
//200 samples at 48kHz for 1/4 cycle 60 Hz noise
reg  ptr_in, ptr_out; 
//make the phase shift register
ram_infer PhaseShifter(read_data, addr_reg, write_data, we, CLOCK_50);	
//////////////////////////////////////////////////////////////////////
/// LMS /////////////////////////////////////////////////////////////
// LMS registers
// 2 weights
reg signed  w1, w2;
// 2 inputs
reg signed  ref60, shifted_ref60 ;
// error output (main output)
wire signed  error_out ;
// two product terms
wire signed  w1_x_ref, w2_x_shifted_ref;
// mult for weight times ref and weight times phase-shifted ref
signed_mult w1xRef(w1_x_ref, w1, ref60);
signed_mult w2xRefShifted(w2_x_shifted_ref, w2, shifted_ref60) ;
//assume noisy signal is on right channel, ref on left channel
assign error_out = {audio_inR, 2'h0} - (w1_x_ref + w2_x_shifted_ref);
//////////////////////////////////////////////////////////////////////
/*
// loopback test
always @ (posedge AUD_DACLRCK)
begin
	audio_outL <= audio_inL;
	audio_outR <= audio_inR;
end
*/
//debug readouts
assign LEDG = state;
assign LEDR = ptr_out;
//Run the state machine FAST so that it completes in one 
//audio cycle
always @ (posedge CLOCK_27)
begin
	if (reset)
	begin
		ptr_out <= 8'h1 ; // beginning of shift register
		ptr_in <= 8'h0 ;
		we <= 1'h0 ; 
		state <= 4'd8 ; //turn off the state machine	
		//last_clk <= 1'h1;
	end
	
	else begin
		case (state)
	
			1: 
			begin
				// set up read ptr_out data
				addr_reg <= ptr_out;
				we <= 1'h0;
				
				// next state
				state <= 4'd2;
			end
	
			2: 
			begin
				//get ptr_out data
				shifted_ref60 <= {read_data, 2'h0} ;
					
				// set up write ptr_in data
				addr_reg <= ptr_in;
				we <= 1'h1;
				write_data <= audio_inL ;
				
				// store current ref channel
				ref60 <= {audio_inL, 2'h0} ;
				
				// make some output
				// original signal in R channel
				// denoised signal in L channel
				// audio seems to negate signal, so invert it
				audio_outR <= -audio_inR ;
				audio_outL <= -error_out;
				
				// next state
				state <= 4'd3;
			end
			
			3:
			begin
				// turn off memroy write
				we <= 1'h0;
				// update weights
				w1 <= w1 + (((ref60)? -error_out : error_out)>>>10) ;
				w2 <= w2 + (((shifted_ref60)? -error_out : error_out)>>>10) ;
				// next state
				state <= 4'd5;
			end
			
			
			5: 
			begin
				// phase shifter pointer control
				// update write pointer
				if (ptr_in == 8'd200) //200
					ptr_in <= 8'h0;
				else
					ptr_in <= ptr_in + 8'h1 ;
					
				// update read pointer
				if (ptr_out == 8'd200)
					ptr_out <= 8'h0;
				else
					ptr_out <= ptr_out + 8'h1 ;
				
				//next state is end state
				state <= 4'd8;
			end
			
			8:
			begin
				// wait for the audio clock and one-shot it
				if (AUD_DACLRCK && last_clk==1)
				begin
					state <= 4'd1 ;
					last_clk <= 1'h0 ;
				end
				// reset the one-shot memory
				else if (~AUD_DACLRCK && last_clk==0)
				begin
					last_clk <= 1'h1 ;
				end	
			end
			
			default:
			begin
				// default state is end state
				state <= 4'd8 ;
			end
		endcase
	end
end	
endmodule
//////////////////////////////////////////////////
//// M4k ram for circular buffer /////////////////
//////////////////////////////////////////////////
// Synchronous RAM 
// modified for 16 bit access
// of 200 words to tune for 1/4 cycle at 60 Hz
module ram_infer (q, a, d, we, clk);
output reg   q;
input  d;
input  a;
input we, clk;
 
reg  mem ;
	always @ (posedge clk) 
	begin
		if (we) mem <= d;
		q <= mem ;
	end
endmodule 
//////////////////////////////////////////////////

in this code they use circular buffer to buffer stream data from the codec (DE2), they use 2 counter for read/write but in state 5, they use both up counter and jusst use one address port for both counter, is it possible ????

shifted_ref60 <= {read_data, 2'h0} ; mean when write by VHDL ????