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zlan01's avatar
zlan01
Icon for New Contributor rankNew Contributor
6 years ago

I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

Can I use the locked output of pll to generate a reset signal for my design? And what is the best reset mode for max10 ?using a input reset or generating a reset signal just in FPGA ？ For my board,t...
SreekumarR_G_Intel's avatar
SreekumarR_G_Intel
Icon for Frequent Contributor rankFrequent Contributor
6 years ago

Hello all,

Sorry i was caught up into different stuff ,

Actually in synthesis world reg [24:0] pup_count = 25'd0; is doesnt mean anything. if you think how you infer this as hardware i am not sure how to design or i can say there should be some define state to make sure it is set to Logic 0 or 1.

I have to check the LRM and Quartus synthesis tool to confrim by deafult the state of the reg type signal.

Also reg [24:0] pup_count = 25'd0; only used in Simulation not use in synthesis.

Hence if you want your design have valid state at reset kindly consider to use external Reset.

Sorry delay in repsonse again.

Thank you,

Regards,

Sree