I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

Nope, I don't like that approach. Can't rely on SYS_CLK being valid if PLL is not locked.

Here is what I do. I generate an async reset at powerup ONLY. Sync to PLL clock via dual rank sync circuit if sync reset is desired instead.

// PowerUP Reset Logic
 
    // generate a 500ms reset pulse on initial powerup
 
`ifdef SIMULATION
    reg [24:0] 		pup_count = 25'd24999900;
`else
    reg [24:0] 		pup_count = 25'd0;
`endif
    reg 		pup_reset = 1'b1;
 
    always @(posedge CLOCK_50)
	begin
	pup_count <= #TPD pup_count + 1'd1;
	if (pup_count == 25'd25000000) pup_reset <= #TPD 1'b0;
	end
 
    wire 		reset = pup_reset;

PLL logic looks like this:

    // Altera PLL Clock module
 
    // Transform external crystal clock to our internal CPU clock
 
    wire 			pll_locked;
    wire 			CLOCK_CPU;
 
    pll pll
	( .inclk0		(CLOCK_50),	// input clock
	  .locked		(pll_locked),	// status output
	  .c0			(CLOCK_CPU)	// output clock
	  );
 
    wire			clk = CLOCK_CPU;