I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

oh,thanks very much!

what about use the output of the pll to driver the reset generation logic ?

Can the code below generate a reset correctly?

always@(posedge sys_clk ) //sys_clk is a output of the pll and is 200Mhz

begin

if(~locked_sig)

reset_cnt <= 30'd0;

else if(reset_cnt < 30'd200_000_005 ) // 1second to configure

reset_cnt <= reset_cnt + 30'd1;

end

assign rst_n = (reset_cnt == 30'd200_000_001)?1'b0:1'b1;