I design a board with max10,and do not design the reset input for max10, how can I generate a internal reset ?

Very simple to do. Init a register to '0' and have it drive the RESET~ signal (ie, an active low reset).

Then have a counter that starts at '0' and counts up for some number of bits (width depends on clock period and desired reset pulse width).

When the counter overflows (or hits some predetermined value) set the register driving RESET~ to a '1', which deasserts reset.

I have used this technique on various parts to, for example, generate a fixed 500ms reset pulse on FPGA powerup/configuration.

No external reset input signal required.

I used the onboard PLL to generate my system clock from the external 50MHz crystal oscillator input. I also used the 50MHz clock input to drive the reset generation logic (so it operates independent of the PLL).