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JScho6
Occasional Contributor
7 years agoIf this is only happening on a few boards, then you're probably looking for a different cause. The defect you're describing may be a latch-up, which means that both the push and the pull driver of the CMOS output are driven at the same time, shorting out the IO voltage to GND.
I have hardly ever seen this on an FPGA. but I've seen it many times on CPLDs, ever since the AMD MACH series. The most likely cause for a latch-up on CPLDs is power spikes and drops. Check voltage ripple and step response on your regulators. You can always improve step response with a larger cap and lower ESR, but with multiple voltages involved on an FPGA board, you may need to go into deeper analysis for possible cross-regulation problems.