Forum Discussion
AlexKucherov
New Contributor
New ContributorHVIO and HSIO inputs during power-up
Hello Intel Team What should be the state of the HVIO and HSIO inputs during unpowered FPGA and power -up and power-down state? Is there any limitations? If there is an issue if the periphera...
JohnT_Altera
Regular Contributor
Regular ContributorHi,
you will need to refer to Agilex 7 General-Purpose IO User Guide https://cdrdv2-public.intel.com/768846/ug-683780-768846.pdf table 3.
