HVIO and HSIO inputs during power-up

Hello Intel Team

What should be the state of the HVIO and HSIO inputs during unpowered FPGA and power -up and power-down state? Is there any limitations?

If there is an issue if the peripheral device powered before the FPGA?

In AN 692: Power Sequencing Considerations for Cyclone® 10 GX,Arria® 10, Stratix® 10, Agilex™ 7, and Agilex™ 5 Devices

Agilex HVIO do not mention – see below