HPS Configuration in QSys: Why is hps_io exported?

DrTobbe you are correct, except the last part. Drive strength and slew rate assignments should take effect, but you hit the nail on the head why those interfaces need to be exposed. The HPS pins in Arria/Cyclone V are limited compared to the FPGA pins so drive strength and slew rate are probably the only assignments you can set, the rest of the I/O features are simply not present.

It's important that you *do not* manually assign the HPS pins because the HPS component in Qsys hands this information off to Quartus already and if you make a conflicting pin location assignment you'll probably get a confusing error message out of Quartus when the compilation fails.