Hi, you are right with regards to the I2C routing (they have dedicated pin location assignment which correlates to actual pins). I may be wrong, but this is how I interpret the need to export the hps_io conduit:
- The same qsys design can be reused in different Cyclone V SoC packages, where the actual pin location may differ from one another
- How does Quartus knows which pins to assign to, in this case?
- By exporting the hps_io pins, you then assign the exposed ports at the top level of the verilog instantiation (for example, I call this verilog instantiation name "soc")
- During full compilation, Quartus looks at the soc module, interprets that pin assignments are needed for the peripherals (I2C) for example, and searches the corresponding pin location that it needs to allocate the peripherals to.
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