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paw_93's avatar
paw_93
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2 years ago
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How well FPGA adjust delays based on .sdc

Hi, I have a question regarding the way the sdc timing constraints affect the design. Imagine a situation where we have a source synchronous design (both directions). FPGA drives flip-flop on the ...
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  • RichardT_altera's avatar
    RichardT_altera
    2 years ago

    Perhaps sstrell could help to clarify more on your first question.

    Anyhow, we uses one of the two methods in deriving the input and output constraints for the SS.
    From what I see in the diagram, you may consider using the system-centric method.

    By specifying the appropriate clock waveform using the -waveform option, you can effectively align the clock edges to accommodate the data transfer requirements. Whether you choose center alignment or edge alignment depends on your specific design needs.

    You may checkout the "Clock and Data Relationship" section in AN433 and below screenshot.

    Regards,

    Richard Tan

RichardT_altera's avatar
RichardT_altera
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2 years ago

We noticed that we haven't received a response from you regarding the latest previous question/reply/answer, and will now transitioning your inquiry to our community support. We apologize for any inconvenience this may cause and we appreciate your understanding.

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Best Regards,

Richard Tan


paw_93's avatar
paw_93
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2 years ago

Hi Richard,

Thank you for your answer. Yes, that answer was helpful. From that I conclude that Intel prefers to use -waveform option instead of -clock_fall in that specific scenarios.

Have a nice day!