Altera_Forum
Honored Contributor
7 years agohow to write SDC timing constraints for an asynchronous interface
Hi all,
Can please some one explain how I can write constraints for an asynchronous interface? The interface is between 8051 and Cyclone FPGA, the signals coming from 8051 are ALE, CE, WR, RD and an 8-bit multiplexed I/O data and address port. This interface is same like the 8051 interfaced with external memory. The following link showing interface of 8051 with external memory http://www.refreshnotes.com/2016/03/8051-external-data-memory-interfacing.html There is no clock input to FPGA. This interface is already working without any timing constraints.