how to write SDC timing constraints for an asynchronous interface

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Hi all,

Can please some one explain how I can write constraints for an asynchronous interface? The interface is between 8051 and Cyclone FPGA, the signals coming from 8051 are ALE, CE, WR, RD and an 8-bit multiplexed I/O data and address port.

This interface is same like the 8051 interfaced with external memory. The following link showing interface of 8051 with external memory

http://www.refreshnotes.com/2016/03/8051-external-data-memory-interfacing.html

There is no clock input to FPGA. This interface is already working without any timing constraints.

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I assume you want the 8051 as master and use fpga ram block as slave. I know fpgas work on clocked design so I suggest you register all signals on an fpga clock internally before the ram. What clock speed depends on the 8051 requrements.

Once you declare clock speed and io delays in sdc you should get a more reliable design