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Altera_Forum
Honored Contributor
15 years agoA PLL has analog components, that can't be represented by "code", the VCO (physically a differential ring oscilator with variable supply voltage), phase detector and loop filter. In some cases, it can be solution to generate a double frequency clock by processing both edges of the input clock with logic gate delay chains or external delay circuits.
The feasibility depends of course on the clock signal specification and available resources.