Forum Discussion
Honored ContributorHow to use the DCFIFO?
Hello i used the megawizard to instantiate a DCFIFO but it seems i can't write anything to the fifo.. my usedw never changes
Anyone has a verilog example of a code that is working??? I tried to let wrreq always at 1 and wrclck changes when i need to write something16 Replies
Altera_ForumYou are right Kaz, i was connecting the wrclk signal wrong in my wrapper ( i was generating one that was customized to my needs and instead of using my signal i was using the rdclk). Two weeks of work because of that :@:@
Thanks a LOT for the help. At least now i am more familiarized with the FIFO- Altera_Forum
oopp sorry. read count is commented out.
I am pretty sure you are either connecting something wrong or reading the wrong signal - Altera_Forum
Hi,
dc fifo is straightforward and doesn't need any particular sequences. reset is not done by many people. I note that you connect to usedw two signals (write and read word counts). This should result in eror or warning at compilation(double drive). You should not do that - Altera_Forum
By the way Josyb or Kaz, any of you have msn or gtalk? it would be easier to talk in a "chat" way.. i really need this working :S
my google contact is andreprado88 at gmail dot com (you can e-mail me also).. thanks - Altera_Forum
Hum i dont reset the fifo, i am only reseting the signals in my FIFOWRAPPER (signals that go inside the fifo)
Do i need to reset the fifo? How does the signals need to be in order to write in the FIFO? Is there a protocol that WRREQ and WRCLK must follow? Can't i just let wrreq at 1 and use a 50mhz clk to write? - Altera_Forum
There is something in the about wrreq being active and the dcfifo coming out of reset. If I see your .stp wrreq is high before the wr and rd clocks start. I couldn't find that you actually reset the dcfifo. I tried to compile your code in order to simulate it (using Quartus II 9.1SP2) but the snippet is not complete.
- Altera_Forum
Hello Kaz, i am using an extra MSB but it stays at 0.
My code is not working :( Can't make a simple DCFIFO work.. Please, could someone give me a hand? Thanks - Altera_Forum
Thanks a lot Kaz i will take a look at 10th Jan (no acess to the kit untill that date)
Merry chrismas and a happy new year =) - Altera_Forum
No, it will read '0' because all bits rollover to zero. If you poll right at the very start you may pick up 0 => 1 => 0 transition.
- Altera_Forum--- Quote Start --- My assumption is that your fifo gets full. When the fpga starts and soon after reset, you are writing into the fifo without reading thus it gets full and the word count will increase from 0 to 128. When 128 the word count cannot represent 128 and rolls back to zero unless you have one extra bit on your word count. The best way is to simulate your design or trigger the signaltap when fifo words is say half (bit[5] '0' => '1') --- Quote End --- I will take a look into that, but my C program is reading the USEDW[2] in pooling mode, if that was the problem it should read 1 constantly instead of 0, right?
