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My assumption is that your fifo gets full.
When the fpga starts and soon after reset, you are writing into the fifo without reading thus it gets full and the word count will increase from 0 to 128. When 128 the word count cannot represent 128 and rolls back to zero unless you have one extra bit on your word count.
The best way is to simulate your design or trigger the signaltap when fifo words is say half (bit[5] '0' => '1')
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I will take a look into that, but my C program is reading the USEDW[2] in pooling mode, if that was the problem it should read 1 constantly instead of 0, right?
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