How to use M9k block memory

I wouldn't recommend doing this if you want to run the interface at any significant speed without placing a standard high speed interface between the two FPGAs.

At the end of the day what type of latencies/throughput/clock speeds are you looking to have in your design? Wiring all the on-chip memory signals through the HSMC connector as a parallel bus may not give you the throughput you are looking for without pipelining and proper timing constraints (remember there is a lot of delay doing chip-to-chip communication)