How to use LVDS?

I think there's some confusion on the terms being used here...

LVDS is a differential I/O standard that specifies voltage levels. There is no specific form of clocking implied by using an LVDS I/O standard. Some Altera devices have native support for LVDS, while some devices require external components (resistors) to get the voltage levels right.

CDR is Clock-Data Recovery. This is a method of extracting (recovering) a clock from a data stream. At higher speeds (generally above 1.25 Gbps), the problems with controlling the relationship between a clock signal and a data signal are great enough that you really need to get the clock from the data transitions.

The scheme where you send the clock along with the data as a separate signal is often called "Clock Forwarding." Interfaces like this (SPI4.2, for example) use one or more data lines and a separate clock. For higher speeds or longer traces or more connectors, you often want to have a way to dynamically adjust the relationship between the forwarded clock and the data lines. Some of the Altera devices have the capability to do this with DPA (Dynamic Phase Alignment).

Going back to your original question, I think you were asking what Cyclone I, II, and III support relative to these terms...

Cyclone I and Cyclone II support LVDS, but only with external resisitors. Cyclone III added a true LVDS output buffer, so you don't need to use external resisitors on the transmitters. However, the resistor required on the receive side is still external for Cyclone III. If you want to use LVDS to communicate with a Cyclone device, you'll probably have to use some sort of clock-forwarding scheme.

CDR is only available in Altera's "GX" devices. There are generally fewer of these transciever channels, though they are able to run much faster than any of the more traditional I/Os (over 6 Gbps). In general, "CDR" and "Cyclone" are two terms that don't go together.

DPA is available in the newer Stratix devices (II and III).

And here's one more I'm throwing in just because I see it misused all the time and I'm on a roll here...

SERDES: This is a circuit that can take fast serial data and convert it to parallel (or vice versa). Having a SERDES does NOT imply that you have CDR. All the Stratix devices have a dedicated SERDES in some of the I/O cells. Cyclone devices use the regular logic to serialize and deserialize the I/O.

I hope that helps. I'm still not sure I answered your question, mostly because I'm not exactly sure what you were asking, but I tried.

Thank u Nick it's very kind of u .

and can you tell me about the follow things of your LVDS?

i wish you will succes in your project!

3-wire?

may be 2 wire and data with clock in CDR.

thank u NICK.

What u said 4 wires ,just 1wire for data 1 wire for different data ,1wire for clock 1wire for clock?

u didn't use encoder for CDR?

and it just use 16 wires for 8bit!

and good luck!

I will try :-) Now I use 18 wires (8 bit data and 2 wires for clock). But in future I'm going to use 16 bit data bus.

Note: CycloneIII has dedicated output buffers for LVDS so no external resistors required.