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Altera_Forum
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17 years ago

How to use global clock network (Stratix)

Hi,

in the "Stratix Device Handbook, Volume 1", page 2-74, it is said that "The global clock networks can also be driven by internal logic . . . ".

That is exactly what I want to do, but i don't know, how.

I have a "generated clock" from the masterclock, by deviding the masterclock by 2. (I know, that I shouldn't do that, and i know, that here are many threads in this forum that are handling this topic, so please concentrate on my main question ;) . . . )

This signal drives a lot of registers in my design. It is working quite well, but I know that it is not nice that this generated clock register has so many fan outs. What I want to do is to feed the output of my clock generating register into a global clock net and all registers that were fed by it now should be fed by this global clock.

What I wanted to do is to use a ALTCLKCTRL megafunction, but it is not supported by my Stratix device. But because the device handbook says, that it is possible, I would like to know, how.

Thanks,

Maik

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  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    I think, the catching of the ADC data is OK because I use the same ADC-data capturing entity in a total different project and I never have any problems there. The ADC data definetely arives correct inside the FPGA . . .

    What makes you think, that I probably don't have a problem with my clk_ena, when you have in mind, that there is a time difference between the clk_ena arriving time in my shift register registers of about 5ns. You also have to keep in mind, that this clk_ena signal has a period shift, as it is derived from the main clock (which it should enable).

    I verified in the simulator (waveform), that I can use the ADC-clock as clk_ena because the period shift can be seen there and everything is all right. BUT that is the shift directly after the toggle flop. Now, this signal is distributed all across the FPGA and on some paths, there is an addition of the above mentioned 5ns. In my oppinion, there could appear an unforseen behaviour.

    That is the fact because I want to have this signal on the global line. I assume that then, the distribution of the signal is much faster. But as I told you, Quartus does not want to switch my signal to the global line . . . .
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    Sorry but we start from very different point of view.

    If all is ok, you don't have the problem but you've it.

    Check it in some way (put a trap in the FPGA to catch your ipotesis), use the signal tap and digital scope to verify that the signal you put in your FPGA are exactly what you expect.

    Check the result and timing error that Quartus gives to you and fix them.

    Told that, Altera Global Lines are global CLOCK lines, so your signal must feed clock port of flip flop, not an enable. It's for that reason that Quartus don't put it on a global line, it can't.

    Good luck
  • Altera_Forum's avatar
    Altera_Forum
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    17 years ago

    As I am at home now, it's unverified what I am writing, but in the Stratix manual (the one i mentioned in my opening message for this thread) it is said, that I can also use register control lines (such as clock enable) on the global signal lines of the FPGA. Also I can chose "Auto Global Register Control Signals" in the assignment editor. I understand that as exactly the signal I want to put on the global line . . . .

    I already tried Signal Tap, but I am not totally satisfied with the results. This might be caused by my unexperience with signal tap. It is very hard to figure out what exactly I can do with signal tap. I promise, I read the whole manual, but I am still full of questions for that tool. . . . .