How to use global clock network (Stratix)

Sorry but we start from very different point of view.

If all is ok, you don't have the problem but you've it.

Check it in some way (put a trap in the FPGA to catch your ipotesis), use the signal tap and digital scope to verify that the signal you put in your FPGA are exactly what you expect.

Check the result and timing error that Quartus gives to you and fix them.

Told that, Altera Global Lines are global CLOCK lines, so your signal must feed clock port of flip flop, not an enable. It's for that reason that Quartus don't put it on a global line, it can't.

Good luck