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Altera_Forum
Honored Contributor
Honored ContributorHow to use global clock network (Stratix)
Hi, in the "Stratix Device Handbook, Volume 1", page 2-74, it is said that "The global clock networks can also be driven by internal logic . . . ". That is exactly what I want to do, but i...
Altera_ForumHonored Contributor
Honored ContributorAs I am at home now, it's unverified what I am writing, but in the Stratix manual (the one i mentioned in my opening message for this thread) it is said, that I can also use register control lines (such as clock enable) on the global signal lines of the FPGA. Also I can chose "Auto Global Register Control Signals" in the assignment editor. I understand that as exactly the signal I want to put on the global line . . . .
I already tried Signal Tap, but I am not totally satisfied with the results. This might be caused by my unexperience with signal tap. It is very hard to figure out what exactly I can do with signal tap. I promise, I read the whole manual, but I am still full of questions for that tool. . . . .
