How to use global clock network (Stratix)

I think, the catching of the ADC data is OK because I use the same ADC-data capturing entity in a total different project and I never have any problems there. The ADC data definetely arives correct inside the FPGA . . .

What makes you think, that I probably don't have a problem with my clk_ena, when you have in mind, that there is a time difference between the clk_ena arriving time in my shift register registers of about 5ns. You also have to keep in mind, that this clk_ena signal has a period shift, as it is derived from the main clock (which it should enable).

I verified in the simulator (waveform), that I can use the ADC-clock as clk_ena because the period shift can be seen there and everything is all right. BUT that is the shift directly after the toggle flop. Now, this signal is distributed all across the FPGA and on some paths, there is an addition of the above mentioned 5ns. In my oppinion, there could appear an unforseen behaviour.

That is the fact because I want to have this signal on the global line. I assume that then, the distribution of the signal is much faster. But as I told you, Quartus does not want to switch my signal to the global line . . . .