Forum Discussion
Joakim
Occasional Contributor
Occasional ContributorHow to use D5_DELAY or D5_OE_DELAY on Cyclone V
I'm desperately trying to get the timing to work between my Cyclone V and an external CPU. Because of the clock delay, it seem to be impossible to get the timing to pass within one clock cycle, so I ...
KhaiChein_Y_Intel
Regular Contributor
Regular ContributorHi,
The total delay is too high, the min delay is 1.7ns and max delay is 3.2ns. The design has timing margin of 5ns which is not enough in this case.
Thanks.
JoakimOccasional Contributor
Occasional ContributorYes, I figured that. But how do I get around it. It can't be unusual to have an interface to a 100 MHz data bus.
I tried multiclock which would give 15 ms timing margin, but in that case it needs a lot more than using single clock.
It seem to be the D5 OE Delay that is set to a value that is too high.
