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Altera_Forum's avatar
Altera_Forum
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18 years ago

how to use cyclone's on-chip-memory?

In my design, I need a 4 ports RAM. The input/output ports are below:

module

ram(data1,waddress1,data2,waddress2,wena,clk,raddress1,raddress2,rena,q1,q2);

input clk,wena,rena;

input [width-1:0] data1,data2;

input [addr:0] waddress1,waddress2;

input [addr:0] raddress1,raddress2;

output [width-1:0] q1,q2;

...

endmodule

I found the 4 ports RAM isn't available in MegaWizard Plug-in of Quartus II.

So I have to code it in my project.

The question is the ram which I coded didn't use the on-chip-memory.

How to use the on-chip-memory with my codes?

4 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    Are the writes to random locations? How do you avoid collisions? If there always to different "sectors" of memory, it might be possible to use an M4K for each sector, and then just mux the address to that sector that is currently using it. (I have no idea what you're doing, so just throwing out suggestions.) Time-multiplexing, if you can meet performance, is the most robust method.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    I actually need two reads and two writes to separate addresses on the same clock.

    THANKS FOR YOUR REPLY!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    18 years ago

    You need to look at the handbook for the device you are targeting and understand what the memories actually look like to properly target them. But in the end, the megawizard is generally a superset of features over what can be targeted with HDL. Whatever device you are targeting, there is no such thing as 4-port RAM. The most any FPGA will have is 2 ports(addresses), both of which are capable to read and write. But there is no true 4-port. Does your design do two reads and two writes to separate addresses on the same clock? If not, you need to multiplex your control signals so they get to the memory when needed. It's also pretty simple to make a 3-port RAM, with one write and two independed reads, just instantiate two memories and have different read addresses for both. The difficult part you'll have is if you need both writes active. You can possibly time-multiplex it or something like that. With most designs, you don't actually need 4 actions per clock, but I could be wrong.