how to use cyclone's on-chip-memory?

You need to look at the handbook for the device you are targeting and understand what the memories actually look like to properly target them. But in the end, the megawizard is generally a superset of features over what can be targeted with HDL. Whatever device you are targeting, there is no such thing as 4-port RAM. The most any FPGA will have is 2 ports(addresses), both of which are capable to read and write. But there is no true 4-port. Does your design do two reads and two writes to separate addresses on the same clock? If not, you need to multiplex your control signals so they get to the memory when needed. It's also pretty simple to make a 3-port RAM, with one write and two independed reads, just instantiate two memories and have different read addresses for both. The difficult part you'll have is if you need both writes active. You can possibly time-multiplex it or something like that. With most designs, you don't actually need 4 actions per clock, but I could be wrong.