how to use another vhdl file's function?

Error (10500): VHDL syntax error at Lab2.vhd(19) near text "=>"; expecting ")", or ","

i just want to input "0001" into bin_in and output from bcd7_out to HEX0 to display a digit number on board

bin2bcd7.vhd

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bin2bcd7 is

Port ( bin_in : in STD_LOGIC_VECTOR (3 downto 0);

bcd7_out : out STD_LOGIC_VECTOR (6 downto 0));

end bin2bcd7;

architecture Behavioral of bin2bcd7 is

begin

with bin_in Select

bcd7_out<=

"1111001"when"0001",

"0100100"when"0010",

"0110000"when"0011",

"0011001"when"0100",

"0010010"when"0101",

"0000010"when"0110",

"1111000"when"0111",

"0000000"when"1000",

"0010000"when"1001",

"0001000"when"1010",

"0000011"when"1011",

"1000110"when"1100",

"0100001"when"1101",

"0000110"when"1110",

"0001110"when"1111",

"1000000"when others;

end Behavioral;