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Altera_Forum
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13 years ago

How to synchronize a PLL with a clock signal

In my design I require there to be a 100 mhz clock signal and a 50 mhz clock signal. I have an 50 mhz clock source so I decided to use a PLL to convert it to a 100 mhz clock. The only issue I have is...
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Altera_Forum
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13 years ago

You don't say whether this clock alignment is needed internal to the FPGA or external to the FPGA.

If it is internal, then just use the 50MHz as the PLL reference, and have the PLL generate *two* output clocks; 100MHz and 50MHz. Those two outputs will be synchronous. The phase of these two signals relative to the input 50MHz will change depending on the PLL mode, but that only matters if you have external logic clocked by the 50MHz reference that you then need to send data from registers clocked by the PLL output signals.

Cheers,

Dave