Forum Discussion
Altera_Forum
Honored Contributor
9 years agoThank you for your responses, I have been looking into this topic for a while and have a few more questions now.
First, as mentioned by FvM, since the quantity is signed and the sign bit is implicit and not counted (the MSb) the format shall become signed Q2.13. Now if I square this, the result would be 32 bits and shall be written as Q4.26? This does not look write as it does not add to 31 but adds to 30 only. What is wrong? It is only today I have found that there are some packages for fixed point arithmatic within VHDL. However, it is not clear to me how old these are or how much support they have in synthesis so I shall have to post a new question. I have only used std_logic_1164 and did not know that there are packages created for supporting fixed point arithmatic.