Forum Discussion
Honored ContributorHow to simulate the FPGA neural network in Altera
I want to simulate the some kind of schematics that work by principle of neural networks. I have Altera Quadrus 11. But when trying create some verilog or vhdl code I see that compilation and simulation items of menu is disabled. Should it due to absence of installed device --such warning is appered when creating the project or I do not entered the license properly. If the issue is in not installed device, which one can I use for my student work, how much space it could take. Can I use the web-edition for this purposes, with or without device?
And the next set of questions relates to the ocding of logical circuit in Altera or Modelsim (which one could I use-- now I have just Model-Sim free edition). The logic circuit should sort analog signals. The other components of circuits is adders with 2 addings and one substraction, and one with adding of all N signals (or non-binary numbers) the N+2 step functions (comparators of amplitude of signals with some x), and one multiplicator and one integrator. So definitive question is the concept and specific of neural networs with back-propagation method in HDL, and other ones is concerning the converting decimal numbers to binary ones (or it could be allowed to be binary from the start), how implement of multiplication for the big coeficent, how the comparator works in Verilog/VHDL, and the most unsure --about integrating the function. I do not exactly even know what is the role of integrator in logic circle (in this case it is connected with the multiplicator and authors even jjust whol ethe whole structure --inverting integrator --*(-Alpha)). Where I could find such examples in VHDL, but it would be better in Verilog, that I studied something. What structure and size of teh whole programming module should be if N (number of sorted items) is 5-6...67 Replies
Altera_ForumI do not know simulink a lot. So I will try to implement it in microcar with the macros of integrator, comparator, adder and so on. But the main issue - shout it be implemented in one cycle or it is needed several iterations. Is it possible to simulate neural network in simulink with the several iterations? As well in altera. As I have just the logic circuit and I need to find the level of shift x that would minimize the function E.
- Altera_Forum
if i were to make a neural network fpga project I would do the following:
1) simulate my model in s- domain (continuous time) in Simulink or Matlab 2) convert to z - domain by choosing an appropriate sampling frequency. Convert my continuous functions into discrete functions in z domain. So an integrator is 1/s in s-domain, but in z-domain it is T/(1-z^-1) where T = 1/sampling frequency. That can be modeled as a simple IIR filter. 3) convert my discrete model into a digital model by using the fixed point toolbox 4) once I've verified that my digital simulink model is stable and converges, I would remodel using Altera's advanced DSP blockset. 5) Once confirm it's functionality, I would let Altera's blockset generate VHDL files 6) Import these VHDL files into my Quartus or Qsys project That maybe a lot more complicated then what you envisioned though... - Altera_Forum
for Example could I simply use code line "An-Amin+x" in verilog for this adder, and integrator *(-Alpha) for the node around the integartor. The fucntion of integartor is dx=x or x-A; so I do understand that x^2/2=x or x-A; or I am not correct as it is integrating for the time, but internal integral seems to be taking into account as far as I remember since mathematics. Or what such (x)=x should mean? if (x) is the derivative?
- Altera_Forum
http://postimg.org/image/m3qrcpqlj/ -- here is the logic circuit that I need to implement. At least in Micro-cap and simulink it should be done without the iterations and Neural Networks. So Could it be donhe in Altera on Verilog. What is the main difficlulties. S --comparator, there is also inverted integartor on time, that multiplies on coeficient alpha(about 1000)--so I do think it could be easier to do in Verilog then Micro-cap for example as there is no libraries for multiplier, even adder, substractor. The only difficult line is integartor..What would you suggested? Sn+2=x-A; Sn+1=x; depending on the K-Sum of Step functions An-X (intial x should be 0--but it is the main bottleneck as x begin rise on some expotential rule). And I am not aware of the fucntion of analog integrator --al other components should be analog, as the source signals should be constant.
- Altera_Forum
Yes I create project not file. But Create not Open.
And you see this circuit in link. It could be created in Simulink and Micro-cap without any iteration--just integrator should be dependent on time. Can I realize such circuit in altera how structure and complex it could be? What main difficulties should be there? - Altera_Forum
And make sure u open a project NOT a file in the Quartus for u to able to compile the project design.
- Altera_Forum
If u are creating a new project,i believe that u already has at least a device family installed in the Quartus because u'll need to choose from the listed part numbers for the design u are creating for.
If u start from a new file instead of new project, then the uninstalled device warning make more sense to me..in order for u to create a design project,compile it and open it again in future the Quartus needs to be installed with the devices. Of course the free web edition has limited feature compared to the subsciption edition.u need to check the altera software download webpage to figure out whether web edition really offers what u are trying to do.
