Forum Discussion
Occasional ContributorHow to simulate a design created in Platform Designer System
As I am comparatively new to Quartus Prime, I would like to know how to simulate my design that is created using Platform Designer System. I would like to elaborate a bit: my counter.v module is converted to a custom IP and I integrated that with an Avalon FIFO IP in platform designer system. Then synchronized all components and then executed "Generated HDL" and "Generate test bench" option in Platform Designer System. Also, I compiled the whole design in Quartus Prime Pro. May I know what I have to do to simulate the whole design? (I have model-sim with my Quartus Prime Pro 18.1.). I have got this doubt since I am using an off the shelf IP (Avalon FIFO IP) and a custom generated IP in my design.
Hi,
The testbench counter_fifo_tb.v that I sent to you before is just an example. If you want to get proper output waveform, you have to change a bit on the stimulus.
Below attached the edited testbench and proper output waveform image. As for the functionality, probably you still need to further verify from your side.
Thanks,
Best Regards,
Sheng
15 Replies
ShengN_alteraSuper Contributor
Hi,
This video and this link https://www.macnica.co.jp/en/business/semiconductor/articles/intel/133550/ will show you how to simulate ip in Quartus Prime Pro Edition. First in Platform Designer, you have to generate the simulation model. Next after full compilation, have to generate combined simulation setup script for IP. Then create a .do file to source the combined simulation setup script and also compiled all the related design files, testbench (Note: testbench need to be created as well). Last, execute macro to run simulation.
Thanks,
Best Regards,
Sheng
p/s: If any answer from the community or Intel Support are helpful, please feel free to give best answer or rate 4/5 survey.
SijithI assume the method in the link above works for a design containing multiple IP's (not just one IP) connected with avalon interfaces (streaming and MM). I am afraid that I could not comprehend well 3:40 of the video posted (In the documentation,
"vlog <compilation options> <design and testbench files> Add command to compile all user design files and testbench files except IP design.)
the testbench files and design files here means the .v files in the "Project Folder/projectname_tb/" folder? And design files from "Project Folder/ip/projectname/projectname_ipcomponent folder/synth" and "Project Folder/projectname/synth" folder ? Also, "except IP design" in above quote means .v files of IP's or .ip files?
My doubt is whether the user have to write some code additionally (like the testbench toplevel module "tb" mentioned in the video, or we just have to collect all necessary codes from different folders (that created while executing "generate testbench" option?) and add them in <design and testbench files> entry in the .do file?
sstrellBest is to see this training first which summarizes your options: https://cdrdv2.intel.com/v1/dl/getContent/653122?explicitVersion=true
- Sijith
As a beginner, I felt bit difficult to follow this the training at a couple of places. I will just list what I understood and please correct me if I got it wrong. I assume BFM is basically a functionality that helps in simulation(?)
My specific case: {I have 2 blocks of IP's (we can call block A and B) in platform designer system. Block A have two IP's (IP_1 and IP_2 that connected though avalon streaming interface. The IP_2 is having avalon MM slave port at one end (the end that connects to block B)). I have a counter in IP_1 and it streams data to IP_2 and which is a FIFO and should pass data to block B through avalon MM interface. The IP_2 and which is a FIFO have a MM read slave that connects to the read master in block B.
I just want to simulate the block A part of the design and see how the output signals from IP_2 FIFO looks like in wave form.}
1) I assume I should follow that sl.no- 29 to 34 in the video. I built a system in the platform designer and I have exported clock and reset to IP_1 which are only input to my design for block A. Also, I have the avalon MM slave port from IP_2 (which is the output from the design of block A). I assume I have to export it in platform designer?
2) Generated testbench system and selected "simple BFM's for clock and reset" . And I have got a _tb.qsys file and got simulation files in _tb folder. Opening _tb.qsys file, I could see clock_bfm and reset_bfm components in platform designer connected to the DUT (for me design of block A).
3) I think I have stuck at how to write test program for my specific case (or its created during the test bench generation?)? Any suggestion? Unfortunately the video regarding this did not help me to comprehend much.
I assume I have to follow same procedure as (?) in sl no. 19 in the video (single IP example) for the combined design also. In sl no. 19 (Avalon MM interface BFM Read/Write operations for Verilog) ( here, I assume in my particular case I should use "Read" option). I did not understand `define MSTR_BFM mstr_test_prog.mstr_bfm_top.mastr_bfm . May I know "mstr_test_prog" is the name of the test program means? (how this name appears?--is it project name?). I assume the .qsys file used is mstr_bfm_top.qsys ? (or it has any other significance?). Also, from where we gets BFM instance name?
Also how we are getting the set_command_<X> (Y) . How we decide what are the things to use in the place of X and Y in the for loop?
Thank you very much.
