How to Setup Constrains for data_in pin to the four D regs with the same delay?

I want to setup constrains for data_in to the four D registers with the same delay, when I design the clock and data recovery logic. The received data goes into fpga from data_in Pin, and directly input to the four D registers. the verilog codes are given below:

dff D1(.d(data_in), .q(a1), .clk(clk), rst(rst));

dff D2(.d(data_in), .q(a2), .clk(clk), rst(rst));

dff D3(.d(data_in), .q(a3), .clk(clk), rst(rst));

dff D4(.d(data_in), .q(a4), .clk(clk), rst(rst));

How to constrain the delay from the input pin data_in to the for registers D1~D4 input the same?

could someone give me some examples?