how to set up table of data to send out serially???

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I'm not a complete newb to Altera/programmable logic, but am by no means an expert... I'm looking for suggestions on how to set up a large table of 'mostly' fixed data in an FPGA, so that I can read from the table and send it out serially. The serial data will be output constantly, simply looping through the table of data. I have the additional complexity of needing to implement up/down counters in a couple table locations (i.e. in a couple locations of the table, I would like to increment/decrement the value each time the entier table is read).

I would like to send out a 'table' of 4,000 8-bit data elements. I would like to generate the data elements in another program (i.e. Excel or similar) and import to my Altera design. I'm mainly stuck on how to set up the table of data, how to then read from it, and how to implement a counter for a couple of the elements (or read from a counter instead of the table for a couple elements)?

Any help would be greatly appreciated!

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You could use a RAM for the data that is not going to change.

The locations that are going to be counters, you would implement using logic elements.

You would use a control state machine to read from the RAM and send data to a serializer block (or UART, if that is what you mean by serial). If you want your counters sent at a specific point in the data stream, you would use address matching logic, eg., every time the RAM address equals zero, rather than reading from the RAM, you read the counter value.

If the contents of the RAM never change, then you can setup the contents using a memory initialization file.

Personally, I'd design it such that you have a dual-ported SRAM, with one side of the RAM implementing an Avalon-MM slave, and then add a set of Avalon-MM slave registers for enabling the controller, and reading status back.

Here's an example with control elements similar to what you want, i.e., getting data from one place, serializing it to another, perhaps you'll get a few ideas:

http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf

Cheers,

Dave

Hi,

I suggest you use a ROM megafunction, which will be initialized with the contents of a MIF file.

(You'll have to convert the data from Excel or whatever into the MIF format, which is a simple one).

Then you'll need to add a bit of logic so that you read from the ocunter instead of the ROM for those addresses.

Thank you very much for the replies Dave and rbugalho! I do appreciate it. I responded yestreday, but apparently it wasn't posted for some reason...

After my initial post I went thru the megafunctions and found the LPM_ROM megafunction, but didn't find much on how to initialize it. Thanks for the initialization comments on the MIF file (memory initialization file). Sound like the simplest method would be with the LPM_ROM block and a state machine to read from ROM or at certain addresses read from a counter...

Also, thank you for the link to your FPGA configuration paper Dave! I will be sending the data out serially along with generating a clock for the data much like you did in the DCLK/DATA generator block (no UART), so that should help with ideas.

I'm curious on your dual-ported SRAM implementation - are you talking external SRAM, or setting up internal memory (using SOPC builder)? And I would still initialize with a MIF file? I've been wanting to get up to speed on SPOC builder (and/or the new tool they're coming out with). I'm not sure I follow on implementing Avalon-MM slave/registers to do this task. Could you elaborate? I have a sneaky suspicion at some point in the future I'll be asked to modify the design to take changes in the table from an external device (i.e. PC), so am thinking the dual-port might make sense there (unless there's a way to change the contents of the ROM externally while the design is running)?

Thanks again for the help gentlemen. I DO appreciate it!!!

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I'm curious on your dual-ported SRAM implementation - are you talking external SRAM, or setting up internal memory (using SOPC builder)?

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Internal memory. You can create your own component that will integrate with SOPC builder.

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And I would still initialize with a MIF file?

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Yes. You could also use the JTAG interface to fill the RAM with initial values. Your SOPC System would consist of a JTAG-to-Avalon-MM master and your RAM component, and control/status registers.

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I've been wanting to get up to speed on SPOC builder (and/or the new tool they're coming out with). I'm not sure I follow on implementing Avalon-MM slave/registers to do this task. Could you elaborate? I have a sneaky suspicion at some point in the future I'll be asked to modify the design to take changes in the table from an external device (i.e. PC), so am thinking the dual-port might make sense there (unless there's a way to change the contents of the ROM externally while the design is running)?

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Once you are familiar with SOPC Builder, the procedure should be obvious ... if its not, then ask on the forum, and you'll get some help.

Get the LPM_ROM version working first, and then generalize it to use dual-ported RAM later.

Cheers,

Dave

Well, I have a deisgn working (in simulation) and want to implement it in h/w. I've been trying to use the bemicro board to do this but am having trouble storing the design in a configuration device. I've posted a thread over in the dev kit area of the forum.

I've implemented this design with a lpm-rom block and a state machine in vhdl, no SOPC or nios. I'm wondering if this might be why I'm having issues seeing the epcs device or implementing a epcs controller for the cyclone III?

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Well, I have a deisgn working (in simulation) and want to implement it in h/w. I've been trying to use the bemicro board to do this but am having trouble storing the design in a configuration device. I've posted a thread over in the dev kit area of the forum.

I've implemented this design with a lpm-rom block and a state machine in vhdl, no SOPC or nios. I'm wondering if this might be why I'm having issues seeing the epcs device or implementing a epcs controller for the cyclone III?

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Before you try storing it, why not simply download the .sof and confirm that it works in hardware? You can 'look' at the design using a SignalTapII instance - use that to confirm the hardware looks like the simulation.

Cheers,

Dave

Hi Dave,

Yep, I was thinking about using Signal Tap to confirm after programming, but my issue with wanting to store the design and load from power-up stems from having to work under XP with the Bemicro drivers and only having Vista/7 at work. I can dual boot my system at home and the older verison is XP, so have been doing a bunch of this at home in the evenings when I have time (been doing a lot of testing out in the field during regular hours).

I did finally figure out how to reach the EPCS and store the design, but never found a single source of documentation from Altera describing all the necessary steps/widgets. Took way longer to figure out than it should have IMHO... (then again maybe I'm just being dense).

When I have a chance again now, I'm going to go thru the SOPC/Nios lab for the bemicro to try to get up to speed on that stuff. I'm sure I'll have more questions then. Thanks for the reply!

Cheers!