Honored Contributor
Honored ContributorThank you very much for the replies Dave and rbugalho! I do appreciate it. I responded yestreday, but apparently it wasn't posted for some reason...
After my initial post I went thru the megafunctions and found the LPM_ROM megafunction, but didn't find much on how to initialize it. Thanks for the initialization comments on the MIF file (memory initialization file). Sound like the simplest method would be with the LPM_ROM block and a state machine to read from ROM or at certain addresses read from a counter... Also, thank you for the link to your FPGA configuration paper Dave! I will be sending the data out serially along with generating a clock for the data much like you did in the DCLK/DATA generator block (no UART), so that should help with ideas. I'm curious on your dual-ported SRAM implementation - are you talking external SRAM, or setting up internal memory (using SOPC builder)? And I would still initialize with a MIF file? I've been wanting to get up to speed on SPOC builder (and/or the new tool they're coming out with). I'm not sure I follow on implementing Avalon-MM slave/registers to do this task. Could you elaborate? I have a sneaky suspicion at some point in the future I'll be asked to modify the design to take changes in the table from an external device (i.e. PC), so am thinking the dual-port might make sense there (unless there's a way to change the contents of the ROM externally while the design is running)? Thanks again for the help gentlemen. I DO appreciate it!!!
