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14 years ago --- Quote Start --- I'm not a complete newb to Altera/programmable logic, but am by no means an expert... I'm looking for suggestions on how to set up a large table of 'mostly' fixed data in an FPGA, so that I can read from the table and send it out serially. The serial data will be output constantly, simply looping through the table of data. I have the additional complexity of needing to implement up/down counters in a couple table locations (i.e. in a couple locations of the table, I would like to increment/decrement the value each time the entier table is read). I would like to send out a 'table' of 4,000 8-bit data elements. I would like to generate the data elements in another program (i.e. Excel or similar) and import to my Altera design. I'm mainly stuck on how to set up the table of data, how to then read from it, and how to implement a counter for a couple of the elements (or read from a counter instead of the table for a couple elements)? Any help would be greatly appreciated! --- Quote End --- You could use a RAM for the data that is not going to change. The locations that are going to be counters, you would implement using logic elements. You would use a control state machine to read from the RAM and send data to a serializer block (or UART, if that is what you mean by serial). If you want your counters sent at a specific point in the data stream, you would use address matching logic, eg., every time the RAM address equals zero, rather than reading from the RAM, you read the counter value. If the contents of the RAM never change, then you can setup the contents using a memory initialization file. Personally, I'd design it such that you have a dual-ported SRAM, with one side of the RAM implementing an Avalon-MM slave, and then add a set of Avalon-MM slave registers for enabling the controller, and reading status back. Here's an example with control elements similar to what you want, i.e., getting data from one place, serializing it to another, perhaps you'll get a few ideas: http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf Cheers, Dave