How to set up Cyclon 10gx transceiver 10g base SR （Short Range 850nm MMF）/LR(Long Range 1310nmSMF )/ER？

HI,

The SR and LR in NativePHY IP basically means short range (chip to chip) setting and long range (chip to backplane) setting irrespective of protocol.

• FPGA to SFP is consider as "chip to chip" connection
• So, you should set it to SR for your case

Regarding BER error debug

• Perhaps you can try enable PHY loopback to isolate is this board related issue or FPGA internal issue first

For the data swap issue and not data corruption issue

• If you look at page 100 on all the PMA/PCS blocked enabled for 10GBASE-R preset.
• https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/hb/cyclone-10/ug_cyclone10_xcvr_phy.pdf
• I don't see any block functionality that can swap data. You may want to check is it your own user logic code issue or maybe Ethernet MAC issue.
• You can also consider to change the payload data pattern to see if it makes a difference or for ease of debug

Thanks.

Regards,

dlim