Forum Discussion
Occasional Contributorhow to set timing constraints for source synchronous inputs
based on AN433 page 43~44.
Question 1:
We define both virtual clock and input clock here.
I think input clock is enough for timing constraint.
Why need both?
Question 2:
We define both input clock and generated clock after pll.
Then we which one should be used for define set_input_delay for data_in?
14 Replies
XQSHENQuestion 4:
I used state machine get output data like below to external spi device.
clk_in = 25MHz -> pll_out = 50MHz -> clk_out = 6.25MHz.
actually, I used counter to get frequency down to 6.25MHz, and output to external device as spi clock.
How can define such kind sdc?
- XQSHEN
based on AN433 page 8~9.
Question 3:
why we need to create unshifted_clock and output_clock in 2 step?
I am not sure what's the purpose of unshifted_clock definition here.
Can we do it as below in 1 step?
create_generated_clock -name out_clock -source [get_pins PLL|inclk[0]] [get_ports clk_out]
