Forum Discussion
XQSHEN
Occasional Contributor
Occasional Contributorhow to set timing constraints for source synchronous inputs
based on AN433 page 43~44.
Question 1:
We define both virtual clock and input clock here.
I think input clock is enough for timing constraint.
Why need both?
Question 2:
We define both ...
XQSHENOccasional Contributor
Occasional ContributorQuestion 4:
I used state machine get output data like below to external spi device.
clk_in = 25MHz -> pll_out = 50MHz -> clk_out = 6.25MHz.
actually, I used counter to get frequency down to 6.25MHz, and output to external device as spi clock.
How can define such kind sdc?
