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XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

how to set timing constraints for source synchronous inputs

based on AN433 page 43~44. Question 1: We define both virtual clock and input clock here. I think input clock is enough for timing constraint. Why need both? Question 2: We define both ...
XQSHEN's avatar
XQSHEN
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Question 4:

I used state machine get output data like below to external spi device.

clk_in = 25MHz -> pll_out = 50MHz -> clk_out = 6.25MHz.

actually, I used counter to get frequency down to 6.25MHz, and output to external device as spi clock.

How can define such kind sdc?